50% Better Perf-Per-Watt, Using Chiplets For First Time

Continuing our coverage of AMD’s 2022 Financial Analyst day, we have the matter of AMD’s forthcoming RDNA 3 GPU architecture and the Navi 3X GPUs that will be built upon it. Up until now, AMD has been fairly quiet about what to expect with RDNA 3, but as RDNA 2 approaches its second birthday and the first RDNA 3 products are slated to launch this year, AMD is offering some of the first significant details on the GPU architecture.

First and foremost, let’s talk about performance. The Navi 3X family, to be built on a 5nm process (TSMC’s, no doubt) is targeting a greater-than 50% performance-per-watt uplift versus RDNA 2. This is a significant and similar uplift as to AMD saw moving from RDNA (1) to RDNA 2. And while such a claim from AMD would have seemed ostentatious two years ago, RDNA 2 has given AMD’s GPU teams a significant amount of renewed credibility.

Thankfully for AMD, the 1-to-2 transition, they don’t have to find a way to come up with a 50% uplift based on architecture and DVFS optimizations alone. The 5nm process means that Navi 3X is getting a full node’s improvement from the TSMC N7/N6 based Navi 2X GPU family. As a result, AMD will see a significant efficiency improvement from that alone.

But with that said, these days a single node jump on its own can’t deliver a 50% perf-per-watt improvement (RIP Dennard scaling). So there are several architecture improvements planned for RDNA 3. This includes the next generation of AMD’s on-die Infinity Cache, and what AMD is terming an optimized graphics pipeline. According to the company, the GPU compute unit (CU) is also being rearchitected, though what degree remains to be seen.

But the biggest news of all on this front is that, confirming a year’s worth of rumors and several patent applications, AMD will be using chiplets with RDNA 3. To what degree, AMD isn’t saying, but the implication is that at least one GPU tier (as we know it) is moving from a monolithic GPU to a chiplet-style design, using multiple smaller chips.

Chiplets are in some respects the holy grail of GPU construction, because they give GPU designers options for scaling up GPUs past today’s die size (reticle) and yield limits. That said, it’s also a holy grail because the massive amount of data that must have passed between different parts of a GPU (on the order of terabytes per second) is very hard to do – and very necessary to do if you want a multi- chip GPU to be able to present itself as a single device. We’ve seen Apple tackle the task by essentially bridging two M1 SoCs together, but it’s never been done with a high-performance GPU before.

Notably, AMD calls this an “advanced” chiplet design. That moniker tends to get thrown around when a chip is being packaged using some kind of advanced, high-density interconnect such as EMIB, which differentiates it from simpler designs such as Zen 2/3 chiplets, which merely route their signals through the organic packaging without any enhanced technologies. So while we’re eagerly awaiting further details of what AMD is doing here, it wouldn’t at all be surprising to find out that AMD is using a form of Local Si Interconnect (LSI) technology (such as the Elevated Fanout Bridge used for the MI200 family of accelerators) to directly and closely bridge two RNDA 3 chiplets.

At this point, AMD isn’t going into any more details on the architecture or Navi 3X GPUs. Today is a teaser and roadmap update for the analyst market, not an announcement of what we can only assume will be the Radeon RX 7000 family of video cards. None the less, with the first RDNA 3 products slated to launch later this year, a more formal announcement cannot be too far away. So we’re looking forward to hearing more about what stands to be a major shake-up in the nature of GPU design and fabrication.